Authors - M. Kamaraju, B. Rajasekhar, V.N.V.R. Karthik, V.N.L. Mahima, Y.H.V. Satya Narayana, R. Pujitha Abstract - This manuscript presents a dedicated Application-Specific Integrated Circuit (ASIC) architecture purpose-designed for computing eigenvalues of two-dimensional square matrices in resource-constrained embedded systems. The fundamental challenge motivating this work stems from the computational intensity of eigenvalue decomposition in digital signal processing, robotics control systems, and embedded analytics, where conventional software implementations incur unacceptable latency and power overhead. The proposed solution lever-ages the closed-form algebraic solution inherent to 2×2 matrices, eliminating iterative numerical methods and their associated performance penalties. Our design employs a direct characteristic-equation approach mapped onto dedicated arithmetic circuits including parallel multipliers, adders, and a specialized square-root computation unit implementing the non-restoring digit-re-currence algorithm. The Verilog RTL synthesized using Cadence Genus in a 180 nm CMOS standard cell library yields a compact silicon footprint of 1,703 square micrometers utilizing 196 standard cells, with measured power dissipation of 0.5738 milliwatts at 100-megahertz operation. Timing closure is achieved with positive slack under worst-case process-voltage-temperature conditions. The high dynamic-to-static power ratio of 98.66 percent to 1.34 percent indicates activity-dominated power behavior, confirming successful implementation of low-leakage design principles. These metrics demonstrate that the proposed architecture constitutes an effective hardware acceleration solution for eigenvalue computation in battery-powered and always-on applications where conventional approaches prove infeasible.
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