Authors - Anirudh P, Nimisha K, Princy P Abstract - As technology advances, circuit complexity increases, integrated cir cuits become more prone to defects during manufacturing and operation. Conse quently, in order to ensure reliable operation, effective testing and stability eval uation of memory cells are essential. Static random-access memory plays a major role in modern digital systems due to its high-speed data access and efficient per formance. However, its reliable functioning is strongly influenced by device level parameters and supply voltage variations. In critical applications, even single fault occurrence may pose serious reliability issues, highlighting the need for ef ficient test methods. Extensive research has been carried out to investigate the static noise margin of SRAM cells. However, the influence of multiple defects has received relatively limited attention in existing literature. This study empha sizes the analysis of multiple defects because their occurrence becomes more fre quent in nano-meter technology regimes. Moreover, these defects can cause sig nificant fault behavior, potentially reducing the stability and reliability of SRAM cells. Multiple defects (Df3-Df3c) and (Df4-Df4c) are selected for analysis as they produce strong fault effects as they occur in the power supply and ground paths of the SRAM cell, which are critical for proper circuit operation. Any dis turbance along these conduction paths alters the effective operating voltage of the cross-coupled inverters and consequently affect the drive capability of the associated transistors. Moreover, the behavior of these defects is examined under various temperature conditions, supply voltages, and process corners in order to assess their overall effect on SRAM cell stability.
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