Authors - Aqdas Hassan, Farooque Azam, and Muhammad Waseem Anwar Abstract - The RISC-V Vector Extension (RVV) enables scalable data-parallel processing through a flexible vector length architecture, offers a standardized and scalable approach to vector computing. Derived from an analysis of existing RVV architectures, this paper presents a focused architectural study and implementation of a basic RVV-based vector extension. Unlike complex, high-performance designs, the proposed architecture prioritizes simplicity and clarity, implementing only essential vector arithmetic and memory instructions. The vector extension is integrated with a single-cycle scalar RISC-V core, and instruction decoding is implemented and verified at RTL level. Functional simulation confirms correctness of RVV instruction decoding. This work bridges the gap between theoretical RVV studies and practical step-by-step hardware implementation.
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